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[ak4440] ak4440 192khz 24-bit 8ch dac with 2vrms output general description the ak4440 is a 5v 24-bit 8ch dac wi th an integrated 2vrms output buffer. a charge pump in the buffer develops an internal negative power supply rail t hat enables a ground-refere nced 2vrms output. using akm?s multi bit modulator architecture, the ak 4440 delivers a wide dynamic range while preserving linearity for improved thd+n perform ance. the ak4440 integrates a comb ination of swit ched-capacitor and continuous-time filters, increas ing performance for systems with excessive clock jitter. the 24-bit word length and 192khz sampling rate make this part ideal for a wide range of consumer audio applications, such as dvd/bd, av receiver, home theater systems and set- top boxes. the ak4440 is offered in a space saving 30pin vsop package. features ? sampling rate ranging from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24bit 8 times fir digital filter with slow roll-off option ? switched-capacitor filter with high tolerance to clock jitter ? single ended 2vrms output buffer ? digital de-emphasis filter: 32khz, 44.1khz or 48khz ? soft mute ? control i/f: 3-wire serial and i 2 c bus ? audio i/f format: msb justified, lsb justified (16bit, 20bit, 24bit), i 2 s, tdm ? master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (normal speed mode) 128fs, 192fs, 256fs or 384fs (double speed mode) 128fs or 192fs (quad speed mode) ? thd+n: -93db ? dynamic range: 105db ? automatic power-on reset circuit ? power supply: +4.5 to +5.5v ? ta = -20 to 85 c ? small package: 30 pin vsop (9.7mm x 7.6mm) ms1088-e-01 2011/03 - 1 -
[ak4440] charge vss2 1 1 pump cn cp vee scf dac lout1 scf dac rout1 scf dac lout2 scf dac rout2 scf dac lout3 scf dac rout3 audio i/f control register ak4440 mclk lrck bick 3-wire or i 2 c sdti1 sdti2 sdti3 pcm scf dac lout4 scf dac rout4 sdti4 lpf lpf lpf lpf lpf lpf lpf lpf vdd vss1 avdd block diagram ms1088-e-01 2011/03 - 2 -
[ak4440] ordering guide ak4440ef -20 +85 c 30pin vsop AKD4440 evaluation board for ak4440 pin layout 6 5 4 3 2 1 mclk bick lrck sdti1 test smute/csn/cad0 7 dif0/cdti/sda 8 vdd vss2 cp cn vee lout1 rout1 lout2 a k4440 top view 10 9 sdti2 sdti3 sdti4 11 tdm0b 12 rout2 lout3 rout3 lout4 25 26 27 28 29 30 24 23 21 22 20 19 acks/cclk/scl dem0 13 i2c/dem1 14 rout4 vss1 18 17 p/s 15 avdd 16 ms1088-e-01 2011/03 - 3 -
[ak4440] pin/function no. pin name i/o function 1 mclk i master clock input pin an external ttl clock shou ld be input on this pin. 2 bick i audio serial data clock pin 3 sdti1 i dac1 audio serial data input pin 4 lrck i l/r clock pin 5 test o test pin. this pin should be open. smute i soft mute pin in parallel mode ?h?: enable, ?l?: disable csn i chip select pin in serial 3-wire mode 6 cad0 i chip address pin in serial i 2 c mode acks i auto setting mode pin in parallel mode ?l?: manual setting mode, ?h?: auto setting mode cclk i control data clock pin in serial 3-wire mode 7 scl control data clock pin in serial i 2 c mode dif0 i audio data interface format pin in parallel mode cdti i control data input pin in serial 3-wire mode 8 sda i/o control data pin in serial i 2 c mode 9 sdti2 i dac2 audio serial data input pin 10 sdti3 i dac3 audio serial data input pin 11 sdti4 i dac4 audio serial data input pin 12 tdm0b i tdm i/f format mode in parallel control mode ?l?: tdm256 mode, ?h?: normal mode 13 dem0 i de-emphasis filter enable pin in parallel mode i2c i control mode select pin in serial mode ?l?: 3-wire serial, ?h?: i 2 c bus 14 dem1 i de-emphasis filter enable pin in parallel mode 15 p/s i parallel/serial select pin (internal pull-up pin, typ 100k ) ?l?: serial control mode, ?h?: parallel control mode 16 avdd - dac analog power supply pin: 4.5v 5.5v 17 vss1 - ground pin 18 rout4 o dac4 rch analog output pin 19 lout4 o dac4 lch analog output pin 20 rout3 o dac3 rch analog output pin 21 lout3 o dac3 lch analog output pin 22 rout2 o dac2 rch analog output pin 23 lout2 o dac2 lch analog output pin 24 rout1 o dac1 rch analog output pin 25 lout1 o dac1 lch analog output pin 26 vee o negative voltage output pin connect to vss2 with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature range . when this capacitor has the polarity, the positive polarity pin should be connected to the vss2 pin. non polarity capacitors can also be used. 27 cn i negative charge pump capacitor terminal pin connect to cp with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature range . when this capacitor has the polarity, the positive polarity pin should be connected to the cp pin. non polarity capacitors can also be used. 28 cp i positive charge pump capacitor terminal pin connect to cn with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature range . when this capacitor has the polarity, the positive polarity pin should be connected to the cp pin. non polarity capacitors can also be used. ms1088-e-01 2011/03 - 4 -
[ak4440] pin/function (continued) no. pin name i/o function 29 vss2 - ground pin 30 vdd - charge pump and dac digital power supply pin: 4.5v 5.5v note: all input pins except for the p/s pin should not be left floating. handling of unused pin the following tables illustrate recommended states for open pins: classification pin name setting analog lout4-1, rout4-1 leave open. sdti4-1 connect to vss2. digital dem0, tdm0b (serial control mode) connect to vdd or vss2. test leave open. absolute maximum ratings (vss1=vss2=0v; note 1 ) parameter symbol min max units power supply vdd avdd -0.3 -0.3 +6.0 +6.0 v v input current (any pins except supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. vss1 and vss2 must be conn ected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 1 ) parameter symbol min typ max units power supply vdd avdd +4.5 +5.0 vdd +5.5 v note 3. vdd and avdd are the same voltage. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. ms1088-e-01 2011/03 - 5 -
[ak4440] analog characteristics (ta=25 c; vdd=avdd = +5.0v; fs=44.1khz; bick=64fs; signal frequency=1khz; 24bit input data; measurement frequency=20hz 20khz; r l 5k ; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics ( note 4 ) fs=44.1khz, bw=20khz -93 -84 db fs=96khz, bw=40khz -92 - db thd+n (0dbfs) fs=192khz, bw=40khz -92 - db dynamic range (-60dbfs with a-weighted, note 5 ) 98 105 db s/n (a-weighted, note 6 ) 98 105 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy dc offset (at output pin) -60 0 +60 mv gain drift 100 ppm/ c output voltage ( note 7 ) 1.97 2.12 2.27 vrms load capacitance ( note 8 ) 25 pf load resistance 5 k power supplies power supply current: ( note 9 ) power supply current: ( note 9 ) normal operation (fs 96khz) normal operation (fs=192khz) power-down mode ( note 10 ) 80 85 20 110 120 100 ma ma a note 4. measured by audio precision (system two). refer to the evaluation board manual. note 5. 98db for 16bit input data note 6. s/n does not depend on input data size. note 7. full-scale voltage (0db). output voltage is proportional to the voltage of avdd, aout (typ.@0db) = 2.12vrms vdd/5. note 8. in case of driving capacitive load, inset a resistor between the output pin and the capacitive load. note 9. the current into vdd and avdd. note 10. the p/s pin is tied to vdd and the all other digita l inputs including clock pins (mclk, bick and lrck) are tied to vss2. ms1088-e-01 2011/03 - 6 -
[ak4440] sharp roll-off filter characteristics (ta = 25 c; vdd=avdd = 4.5 5.5v; fs = 44.1khz; de m = off; slow = ?0?) parameter symbol min typ max units digital filter passband 0.05db ( note 11 ) -6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 11 ) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 12 ) gd - 19.3 - 1/fs digital filter + scf + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.05 0.05 0.05 - - - db db db note 11. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 12. the calculating delay time which occurred by digi tal filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. slow roll-off filter characteristics (ta = 25 c; vdd=avdd = 4.5~5.5v; fs = 44.1khz; dem = off; slow = ?1?) parameter symbol min typ max units digital filter passband 0.04db ( note 13 ) -3.0db pb 0 - 18.2 8.1 - khz khz stopband ( note 13 ) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay ( note 12 ) gd - 19.3 - 1/fs digital filter + scf + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0.1/-4.3 +0.1/-3.3 +0.1/-3.7 - - - db db db note 13. the passband and stopband frequencies scale with fs. for example, pb = 0.185fs (@ 0.04db), sb = 0.888fs. dc characteristics (ta = 25 c; vdd=avdd = 4.5 5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v low-level output voltage dif0/cdti/sda (iout = 3ma) vol - 0.4 v v input leakage current ( note 14 ) iin - - 10 a note 14. the current of the p/s pin is not included. the p/s pin has an internal pull-up resistor (typ.100k ? ). ms1088-e-01 2011/03 - 7 -
[ak4440] switching characteristics (ta = 25 c; vdd=avdd= +4.5 +5.5v; c l = 20pf) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 36.864 60 mhz % lrck frequency normal mode (tdm0= ?0?, tdm1= ?0?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % tdm256 mode (tdm0= ?1?, tdm1= ?0?) normal speed mode high time low time fsn tlrh tlrl 8 1/256fs 1/256fs 48 khz ns ns tdm128 mode (tdm0= ?1?, tdm1= ?1?) normal speed mode double speed mode high time low time fsn fsd tlrh tlrl 8 60 1/128fs 1/128fs 48 96 khz khz ns ns audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge ( note 15 ) lrck edge to bick ? ? ( note 15 ) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 81 30 30 20 20 10 10 ns ns ns ns ns ns ns control interface timing (3-w ire serial control mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 16 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 15. bick rising edge must not occur at the same time as lrck edge. note 16. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 17. i 2 c-bus is a trademark of nxp b.v. ms1088-e-01 2011/03 - 8 -
[ak4440] timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 1. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 2. audio serial interface timing ms1088-e-01 2011/03 - 9 -
[ak4440] tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh figure 3. write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh figure 4. write data input timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 5. i 2 c bus mode timing ms1088-e-01 2011/03 - 10 -
[ak4440] operation overview system clock the external clocks, which are required to operate th e ak4440, are mclk, lrck an d bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks bit = ?0?: register 00h), the sampling speed is set by dfs1-0 bits ( table 1 ). the frequency of mclk for each sampling speed is set automatically. ( table 2 ~ table 4 ) in auto setting mode (acks bit = ?1?: default), as mclk frequency is detected automatically ( table 5 ), and the internal master clock becomes the appropriate frequency ( table 6 ), it is not necessary to set dfs1-0 bits. in parallel control mode, the sampling speed can be set by only the acks pin. when acks pin = ?l?, the ak4440 operates by normal speed mode. when acks pin = ?h?, auto setting mode is enabled. the parallel control mode does not support 128fs and 192fs of double speed mode. the ak4440 is automatically placed in power saving mode when mclk, l rck and bick stop during normal operation mode, and the analog output is forced to 0v(typ). when mclk, lrck and bick are input again, the ak4440 is powered up. after power-u p, the ak4440 is in the power-down mode until mclk, lrck and bick are input. dfs1 bit dfs0 bit sampling rate (fs) 0 0 normal speed mode 8khz~48khz (default) 0 1 table 1. sampling speed (manual setting mode) double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz lrck mclk bick fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 36.8640mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz n/a 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz n/a 3.0720mhz table 2. system clock example (normal speed mode @manual setting mode) (n/a: not available) ms1088-e-01 2011/03 - 11 -
[ak4440] lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 3. system clock example (double speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 4. system clock example (quad speed mode @manual setting mode) mclk sampling speed 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 5. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - quad - - table 6. system clock example (auto setting mode) ms1088-e-01 2011/03 - 12 -
[ak4440] audio serial interface format in parallel control mode, the dif0 and tdm0b pins as shown in table 7 can select four serial data modes. the register value of dif0 and tdm0b bits are ignored. in serial control mode, the dif2-0 and tdm1-0 bits shown in table 8 can select 11 serial data modes. initial value of dif2-0 bits is ?010?. in all modes the serial data is msb-first, 2?s complement format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. in parallel control mode, when the tdm0b pin = ?l?, the audio interface format is tdm256 mode ( table 7 ). the audio data of all dacs (eight channels) are i nput to the sdti1 pin. the input data to sdti2-4 pins are ignored. bick should be fixed to 256fs. in serial control mode, when the tdm0 bit = ?1? and the tdm1 bit = ?0?, the audio interface format is tdm256 mode ( table 8 ), and the audio data of all dacs (eight channels) are input to the sdti1 pin. the input data to the sdti2-4 pins are ignored. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be at least 1/256fs. the audio data is msb-first, 2?s complement format. the input data to the sdti1 pin is latched on the rising edge of bick. in tdm128 mode (tdm1-0 bits = ?11?, table 8 ), the audio data of dacs (four channels; l1, r1, l2, r2) are input to the sdti1 pin. the other four data (l3, r3, l4, r4) are input to the sdti2 pin. the input data to sdti3-4 pins are ignored. bick should be fixed to 128fs. the audio data is msb-first, 2?s complement format. the input data to sdti1-2 pins are latched on the rising edge of bick. mode tdm0b pin dif0 pin sdti format lrck bick figure 2 h l 24-bit msb justified h/l 48fs figure 8 normal 3 h h 24-bit i 2 s compatible l/h 48fs figure 9 5 l l 24-bit msb justified 256fs figure 10 tdm256 6 l h 24-bit i 2 s compatible 256fs figure 11 table 7. audio data formats (parallel control mode) mode tdm1 bit tdm0 bit dif2 bit dif1 bit dif0 bit sdti format lrck bick figure 0 0 0 0 0 0 16-bit lsb justified h/l 32fs figure 6 1 0 0 0 0 1 20-bit lsb justified h/l 40fs figure 7 2 0 0 0 1 0 24-bit msb justified h/l 48fs figure 8 3 0 0 0 1 1 24-bit i 2 s compatible l/h 48fs figure 9 normal 4 0 0 1 0 0 24-bit lsb justified h/l 48fs figure 7 0 1 0 0 0 n/a 0 1 0 0 1 n/a 5 0 1 0 1 0 24-bit msb justified 256fs figure 10 6 0 1 0 1 1 24-bit i 2 s compatible 256fs figure 11 tdm256 7 0 1 1 0 0 24-bit lsb justified 256fs figure 12 1 1 0 0 0 n/a 1 1 0 0 1 n/a 8 1 1 0 1 0 24-bit msb justified 128fs figure 13 9 1 1 0 1 1 24-bit i 2 s compatible 128fs figure 14 tdm128 10 1 1 1 0 0 24-bit lsb justified 128fs figure 15 table 8. audio data formats (serial control mode) (n/a: not available) ms1088-e-01 2011/03 - 13 -
[ak4440] sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 01 4 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 1514 6543210 lch data rch data figure 6. mode 0 timing sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 7. mode 1/4 timing lrck bick ( 64fs ) sdti 02 2 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 22 4 23 30 22 1 0 don?t care 23 22 23 figure 8. mode 2 timing ms1088-e-01 2011/03 - 14 -
[ak4440] lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 22 4 23 25 22 1 0 don?t care 23 23 figure 9. mode 3 timing lrck bick(256fs) sdti1(i) 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 23 23 23 23 23 23 23 23 23 figure 10. mode 5 timing lrck bick(256fs) sdti1(i) 256 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 23 0 l4 32 bick 23 0 r4 32 bick 23 figure 11. mode 6 timing lrck bick(256fs) sdti1(i) 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 23 23 23 23 23 23 23 23 23 figure 12. mode 7 timing ms1088-e-01 2011/03 - 15 -
[ak4440] lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 figure 13. mode 8 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 figure 14. mode 9 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 figure 15. mode 10 timing ms1088-e-01 2011/03 - 16 -
[ak4440] analog output block the internal negative power supply generation circuit ( figure 16 ) provides a negative power supply for the internal 2vrms amplifier. it allows the ak4440 to output an audio signal centered at vss (0v, typ) as shown in figure 17 . the negative power generation circuit ( figure 16 ) needs 1.0 f low esr (equivalent series resistance) capacitors (ca, cb). if this capacitor is polarized, the positive polarity pin sh ould be connected to the cp and vss2 pins. this circuit operates by clocks generated from mclk. when mclk stops, the ak4440 is placed in the reset mode automatically and the analog outputs settle to vss (0v, typ). vdd charge pump cp cn vss2 vee 1uf 1uf negative power a k4440 ( + ) cb ca (+) figure 16. negative po wer generation circuit lout a k4440 ( rout ) 0v 2.12vrms figure 17. audio signal output de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15 s). for double speed and quad speed modes, the digital de-emphasis filter is always off. in serial control mode, the dem1 -0 bits are valid for the dac enabled by the dema-d bits ( table 9 ). in parallel control mode, dem1-0 pins are valid ( table 10 ). dem1 bit dem0 bit mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 9 de-emphasis filter control in se rial control mode (normal speed mode) ms1088-e-01 2011/03 - 17 -
[ak4440] dem1 pin dem0 pin mode l l 44.1khz l h off (default) h l 48khz h h 32khz table 10 de-emphasis filter control in pa rallel control mode (normal speed mode) soft mute operation soft mute operation is performed in the digital domain. when the smute pin/bit is set ?1?, the output signal is attenuated to - in 1024 lrck cycles. when the smute pin/bit is returned to ?0?, the mu te is cancelled and the output attenuation gradually changes to 0db in 1024 lrck cy cles. if the soft mute is cancelled within the 1024 lrck cycles after starting this operation, the attenuation is discontinued and it is returned to 0db by the same cycle. soft mute is effective for changing the signal source without stopping the signal transmission. smute pin/bit attenuation dzf pin 1024/fs 0db - lout/rout 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the time for input data to be attenuated to - , is normal speed mode: 1024 lrck cycles (1024/fs). double speed mode: 2048 lrck cycles (2048/fs). quad speed mode: 4096 lrck cycles (4096/fs). (2) the analog output corresponding to a sp ecific digital input has group delay, gd. (3) if soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level in the same cycle. figure 18. soft mute function ms1088-e-01 2011/03 - 18 -
[ak4440] system reset the ak4440 is in power down mode upon power-up. the mlck should be input after the power supplies are ramped up. the ak4440 is in power-dow n mode until lrck are input. mclk power supply (vdd, avdd) charge pump circuit vee pin power down power-up 0v reset 20 s (3) 10ms (max) internal reset reset release (2) time a audio circuit power-up 8~10 lrck clocks (5) d/a out (analog) mute ( d/a out ) d/a in (digital) ?0? data 0v a ctive ( d/a out ) (4) t w<20ms 0.8xvdd 0.3v (1) notes: (1) the ak4440 includes an internal power on reset circuit which is used reset the digital logic into a default state after power up. therefore, the power supply voltage must reach 80% vdd from 0.3v in less than 20msec. (2) register writings are valid after 10ms (max). (3) when internal reset is released, appr oximately 20us after a mclk input, the in ternal analog circuit is powered-up. (4) the digital circuit and charge pump circuit are powered-up in 8~10 lrck cycles when the analog circuit is powered-up. (5) the charge pump counter starts after the charge pump ci rcuit is powered-up. the dac ou tputs a valid analog signal after time a. time a = 1024/(fs x 16): normal speed mode time a = 1024/(fs x 8): double speed mode time a = 1024/(fs x 4): quad speed mode figure 19. system reset diagram ms1088-e-01 2011/03 - 19 -
[ak4440] reset function when the mclk, lrck or bick stops, the ak4440 is placed in reset mode an d its analog outputs are set to vss (0v, typ). when the mclk, lrck and bick are restarted, the ak4440 returns to normal operation mode. n ormal operation internal state reset normal operation gd d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (3) vss (4) mclk or bick or lrck stop (5) (5) (1) (2) notes: (1) clocks (mclk, bick, lrck) can be stopped in the reset mode (mclk or lrck or bick is stopped). (2) the ak4440 detects the stop of lrck or bick if lrck or bick stops for more than 2048/fs. when lrck is stopped, the ak4440 exits reset mode after lrck is inputted. when bick is stopped, the ak4440 exits reset mode after bick is input. (3) digital data can be stopped. the click noise after mclk, lrck and bick are input again can be reduced by inputting the ?0? data during this period. (4) the analog output corresponding to a specific digital input has group delay (gd). (5) no audible click noise occu rs under normal conditions. figure 20. reset timing example ms1088-e-01 2011/03 - 20 -
[ak4440] register control interface the ak4440?s functions are controlled by registers. two type s of control mode write internal registers. in the i 2 c-bus mode, the chip address is determined by the state of the cad0 pin. in 3-wire mode, the chip address is fixed to ?11?. writing ?0? to the rstn bit resets the internal ti ming circuit, but the registers are not initialized. * the ak4440 does not support read commands. * when the state of the p/s pin is changed, the ak4440 should be reset by the rstb bit = ?0?. * in serial control mode, the setting of parallel pins is invalid. function parallel control mode serial control mode double sampling mode at 128/192fs - x de-emphasis x x smute x x 16/20/24bit lsb justified format - x tdm256 mode x x tdm128 mode - x table 11 function table (x: available, -: not available) (1) 3-wire serial control mode (i2c pin = ?l?) the 3-wire p interface pins, csn, cclk and cdti, write internal re gisters. the data on this interface consists of chip address (2bits, c1/0; fixed to ?11?), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits ). the ak4440 latches the data on the ri sing edge of cclk, so data should clocked in on the falling edge. the writing of data becomes va lid by the rising edge of csn. the clock speed of cclk is 5mhz (max). cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d 5 d6d7 a1a2a3a4 r/w c0 a0 d0d1 d2d3 c1-c0: chip address (fixed to ?11?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 21. control i/f timing ms1088-e-01 2011/03 - 21 -
[ak4440] (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4440 supports the fast-mode i 2 c-bus system (max: 400khz). figure 22 shows the data transfer sequence at the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 26 ). after the start condition, a slave address is sent. th is address is 7 bits long followed by th e eighth bit which is a data direction bit (r/w) ( figure 23 ). the most significant six bits of the slave addr ess are fixed as ?001001?. the next one bit is cad0 (device address bit). th e bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) set them. if the slave address match that of the ak4440 and r/w bit is ?0?, the ak4440 generates an acknowledge and the write operation is executed. if r/w bit is ?1?, the ak4440 does not answer any acknowledge ( figure 27 ). the second byte consists of the address for control register s of the ak4440. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 24 ). those data after the second byte contain control data. the format is msb first, 8bits ( figure 25 ). the ak4440 generates an acknowledge after eac h byte is received. a data transfer is always terminated by a stop condition generated by the master. a low to high tran sition on the sda line while scl is high defines stop condition ( figure 26 ). the ak4440 is capable of more than one byte write operation by one sequence. after receipt of the third byte, the ak4440 generates an acknowledge, and awaits the next data . the master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the addresses exceed 03h prior to generating the stop co ndition, the address counter will ?roll ove r? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 28 ) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w a c k figure 22. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 1 cad0 r/w (this cad0 should match with cad0 pin) figure 23. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 24. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 25. byte structure after the second byte ms1088-e-01 2011/03 - 22 -
[ak4440] scl sda stop condition start condition s p figure 26. start and stop conditions scl from master acknowledge data output by master data output by slave(ak4440) 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 27. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 28. bit transfer on the i 2 c-bus ms1088-e-01 2011/03 - 23 -
[ak4440] register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks tdm1 tdm0 dif2 dif1 dif0 0 rstn 01h control 2 rrst 0 slow dfs1 dfs0 dem1 dem0 smute 02h power down control 0 0 0 0 pw4 pw3 pw2 pw1 03h dem control 0 0 0 0 dema demb demc demd note: for addresses from 04h to 1fh, data must not be written. do not write the registers within 10msec after the power supplies are fed. all data can be written to the registers even if pw1-4 and rstn bits are ?0?. when rstn bit goes to ?0?, only inte rnal timing is reset, and the register s are not initialized to their default values. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks tdm1 tdm0 dif2 dif1 dif0 0 rstn default 1 0 0 0 1 0 0 1 rstn: internal timing reset 0: reset. any registers are not initialized. 1: normal operation dif2-0: audio data interface modes ( table 8 ) default: ?010? tdm0-1: tdm mode select mode tdm1 tdm0 bick sdti sampling speed normal 0 0 32fs 1-4 normal, double, quad speed tdm256 0 1 256fs fixed 1 normal speed tdm128 1 1 128fs fixed 1-2 normal, double speed acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this cas e, the setting of dfs1-0 bits is ignored. when this bit is ?0?, dfs1-0 bits set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 rrst 0 slow dfs1 dfs0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted dem1-0: de-emphasis response ( table 9 , table 10 ) default: ?01?, off dfs1-0: sampling speed control ( table 1 ) 00: normal speed 01: double speed ms1088-e-01 2011/03 - 24 -
[ak4440] 10: quad speed when changing between normal/double speed mode and quad speed mode, some click noise occurs. slow: slow roll-off filter enable 0: sharp roll-off filter 1: slow roll-off filter rrst: all registers are initialized. 0: normal operation 1: reset. all registers are initialized. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h power down control 0 0 0 0 pw4 pw3 pw2 pw1 default 0 0 0 0 1 1 1 1 pw4-1: power-down control (0: power-down, 1: power-up) pw1: power down control of dac1 pw2: power down control of dac2 pw3: power down control of dac3 pw4: power down control of dac4 addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h dem control 0 0 0 0 dema demb demc demd default 0 0 0 0 0 0 0 0 dema-d: de-emphasis enable bit of dac1/2/3/4 0: disable 1: enable ms1088-e-01 2011/03 - 25 -
[ak4440] system design figure 29 and figure 30 show the system connection diagram. th e evaluation board (AKD4440) demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. bick 2 sdti1 3 lrck 4 test 5 smute 6 a cks 7 dif0 8 sdti2 9 sdti3 10 sdti4 11 tdm0b 12 dem0 13 vss2 29 cp 28 cn 27 vee 26 mode- setting ak4440 14 15 dem1 p/s analog ground digital ground master clock fs 24bit audio data 64fs 24bit audio data 24bit audio data mclk 1 vdd 30 24bit audio data mode- setting lout1 25 rout1 24 lout2 23 rout2 22 lout3 21 rout3 20 19 18 lout4 rout4 l2ch out r2ch out l3ch out r3ch out l4ch out r4ch out r1ch out l1ch out vss1 17 avdd 16 a nalog 5v + 0.1u 10u 0.1u + 10u 1u (1) + 1u (1) + a nalog 5v figure 29. typical connection di agram (parallel control mode) notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be ad ded in series between aout and capacitive load. - the capacitor of low esr should be used to the capacito r (1). when it uses the cap acitor with the polarity, the positive pole of the capacitor should be connected to cp pin and vss2 pin. - all input pins except for the p/s pin should not be left floating. ms1088-e-01 2011/03 - 26 -
[ak4440] bick 2 sdti1 3 lrck 4 test 5 csn 6 cclk 7 cdti 8 sdti2 9 sdti3 10 sdti4 11 tdm0b 12 dem0 13 vss2 29 cp 28 cn 27 vee 26 micro- controller ak4440 14 15 i2c p/s analog ground digital ground master clock fs 24bit audio data 64fs 24bit audio data 24bit audio data mclk 1 vdd 30 24bit audio data lout1 25 rout1 24 lout2 23 rout2 22 lout3 21 rout3 20 19 18 lout4 rout4 l2ch out r2ch out l3ch out r3ch out l4ch out r4ch out r1ch out l1ch out vss1 17 avdd 16 a nalog 5v + 0.1u 10u 0.1u + 10u 1u (1) + 1u (1) + a nalog 5v figure 30. typical connection diag ram (3-wire serial control mode) notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be ad ded in series between aout and capacitive load. - the capacitor of low esr should be used to the capacito r (1). when it uses the cap acitor with the polarity, the positive pole of the capacitor should be connected to cp pin and vss2 pin. - all input pins except for the p/s pin should not be left floating. ms1088-e-01 2011/03 - 27 -
[ak4440] 1. grounding and power supply decoupling vdd and avdd are supplied from the analog supply and should be separated from the system digital supply. decoupling capacitors, especially 0.1 f ceramic capacitors for high frequency bypass, should be placed as near to vdd and avdd as possible. the vss1 and vss2 must be connected to the same analog ground plane. power-up sequence between vdd and avdd is not critical. 2. analog outputs the analog outputs are single-ended and centered around the vss (ground) voltage. the output signal range is typically 2.12vrms (typ @avdd=5v). the intern al switched-capacitor filter (scf) and continuous-time filter (ctf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. using single a 1 st -order lpf ( figure 31 ) can reduce noise beyond the audio passband. the output voltage is a pos itive full scale for 7fffffh (@ 24bit data) and a negative fu ll scale for 800 000h (@24bit data). the ideal output is 0v (vss) voltage for 000000 h (@24bit data). the dc offset is 60mv or less. aout 560 3.3nf ak4440 2.12vrms (typ) analog out (fc = 86.1khz, gain = -0.85db @ 40khz, gain = -2.70db @ 80khz) figure 31. external 1 st order lpf circuit example1 ms1088-e-01 2011/03 - 28 -
[ak4440] package detail a note: dimension "*" does not include mold flash. 0.22 0.1 0.65 *9.7 0.1 1.5max a 1 15 16 30 30pin vsop (unit: mm) 5.6 0.1 7.6 0.2 0.45 0.2 -0.05 +0.10 0.3 0.15 0.12 m 0.08 1.2 0.10 0.10 +0.10 -0.05 package & lead frame material package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatment: solder (pb free) plate rohs compliance *all integrated circuits form asahi kasei microdevices corporation (akm) assembled in ?lead-free? packages are fully compliant with rohs. ms1088-e-01 2011/03 - 29 -
[ak4440] marking akm ak4440ef xxxbyyyyc xxxbyyyyc date code identifier xxxb: lot number (x: digit number, b: alpha character) yyyyc: assembly date (y: digit number, c: alpha character) revision history date (yy/mm/dd) revision reason page contents 09/10/15 00 first edition 11/03/01 01 error correction 28 1. grounding and power supply decoupling the description was changed. ms1088-e-01 2011/03 - 30 -
[ak4440] important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these product s, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distri butors as to current status of the products. z descriptions of external circuits, ap plication circuits, software and other related information contained in this document are provided only to illustra te the operation and application exam ples of the semiconductor products. you are fully responsible for the incorporation of these ex ternal circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm a ssumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems contai ning them, may require an export license or other official approval under the law and regulations of the country of export pertaining to cust oms and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, di sposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and a ll responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. ms1088-e-01 2011/03 - 31 -

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